{"id":209,"date":"2010-05-09T19:41:45","date_gmt":"2010-05-09T22:41:45","guid":{"rendered":"http:\/\/cursos.unipampa.edu.br\/cursos\/ppgee\/?page_id=209"},"modified":"2020-08-03T10:56:20","modified_gmt":"2020-08-03T13:56:20","slug":"projeto-de-circuitos-eletronicos-integrados","status":"publish","type":"page","link":"https:\/\/cursos.unipampa.edu.br\/cursos\/ppgee\/?page_id=209","title":{"rendered":"Projeto de Circuitos Eletr\u00f4nicos Integrados"},"content":{"rendered":"<h4>C\u00f3digo: AL5012<\/h4>\n<h4>Obrigat\u00f3ria: n\u00e3o<\/h4>\n<h4>Carga-hor\u00e1ria: 60h<\/h4>\n<h4>Cr\u00e9ditos: 4<\/h4>\n<h4><strong>Ementa:<\/strong><\/h4>\n<p>Transistores MOS e portas l\u00f3gicas b\u00e1sicas. L\u00f3gica de chaves. L\u00f3gica est\u00e1tica CMOS e l\u00f3gica din\u00e2mica. Tecnologia de fabrica\u00e7\u00e3o de circuitos<br \/>\nintegrados CMOS. Regras de projeto. Estimativa de desempenho. Pot\u00eancia e atraso em circuitos CMOS. Estilos de layout. Blocos de mem\u00f3ria RAM e<br \/>\nROM. Estrat\u00e9gias de projeto. Gera\u00e7\u00e3o autom\u00e1tica de layout. No\u00e7\u00f5es de s\u00edntese autom\u00e1tica.<\/p>\n<h4>Bibliografia:<\/h4>\n<ul>\n<li>RABAEY, J.; CHANDRAKASAN, A.; NIKOLIC, B. Digital Integrated Circuits: a design perspective. [s.l.]: Pearson Education International, 2003.<\/li>\n<li>WESTE, N.; HARRIS D. CMOS VLSI design: a circuits and systems perspective. 3. ed. [s.l.]:Addison Wesley, 2005.<\/li>\n<li>GRAY, P.; HURST, P.; LEWIS et al. Analysis and Design of Analog Integrated Circuits. [s.l.]: Wiley, 2001.<\/li>\n<li>Artigos cient\u00edficos publicados nas revistas: IEEE Design &amp; Test of Computers, IEEE Journal of Solid-State Circuits, IEEE Computer-Aided Design of Integrated Circuits and Systems.<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>C\u00f3digo: AL5012 Obrigat\u00f3ria: n\u00e3o Carga-hor\u00e1ria: 60h Cr\u00e9ditos: 4 Ementa: Transistores MOS e portas l\u00f3gicas b\u00e1sicas. L\u00f3gica de chaves. L\u00f3gica est\u00e1tica CMOS e l\u00f3gica din\u00e2mica. Tecnologia de fabrica\u00e7\u00e3o de circuitos integrados CMOS. Regras de projeto. Estimativa de desempenho. Pot\u00eancia e atraso em circuitos CMOS. Estilos de layout. Blocos de mem\u00f3ria RAM e ROM. Estrat\u00e9gias de projeto. &hellip; <a href=\"https:\/\/cursos.unipampa.edu.br\/cursos\/ppgee\/?page_id=209\" class=\"more-link\">Continue lendo <span class=\"screen-reader-text\">Projeto de Circuitos Eletr\u00f4nicos Integrados<\/span> <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":23,"featured_media":0,"parent":2013,"menu_order":0,"comment_status":"open","ping_status":"closed","template":"","meta":[],"_links":{"self":[{"href":"https:\/\/cursos.unipampa.edu.br\/cursos\/ppgee\/index.php?rest_route=\/wp\/v2\/pages\/209"}],"collection":[{"href":"https:\/\/cursos.unipampa.edu.br\/cursos\/ppgee\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/cursos.unipampa.edu.br\/cursos\/ppgee\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/cursos.unipampa.edu.br\/cursos\/ppgee\/index.php?rest_route=\/wp\/v2\/users\/23"}],"replies":[{"embeddable":true,"href":"https:\/\/cursos.unipampa.edu.br\/cursos\/ppgee\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=209"}],"version-history":[{"count":3,"href":"https:\/\/cursos.unipampa.edu.br\/cursos\/ppgee\/index.php?rest_route=\/wp\/v2\/pages\/209\/revisions"}],"predecessor-version":[{"id":1356,"href":"https:\/\/cursos.unipampa.edu.br\/cursos\/ppgee\/index.php?rest_route=\/wp\/v2\/pages\/209\/revisions\/1356"}],"up":[{"embeddable":true,"href":"https:\/\/cursos.unipampa.edu.br\/cursos\/ppgee\/index.php?rest_route=\/wp\/v2\/pages\/2013"}],"wp:attachment":[{"href":"https:\/\/cursos.unipampa.edu.br\/cursos\/ppgee\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=209"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}